Circuit Notation as a Programming Language

A diagram is an ordered program

A circuit diagram is a compact syntax for state evolution. Time runs left to right. Each horizontal wire is a qubit register. A box on one wire applies a one-qubit unitary there while the identity acts on every other wire. A vertical controlled operation applies one joint multi-qubit unitary whose action depends on the control's basis value.

The habit that makes circuits readable is to expand them into a sequence:

1. Initialize every wire, usually to $|0⟩$.
2. Apply each one-qubit gate in left-to-right order.
3. Apply each controlled gate as one joint operation on the full state.
4. Measure the selected wires.
5. Record the classical bits.

That sequence can be traced by hand, simulated with a statevector, or compiled through an SDK — three executions of the same program at three levels of fidelity.

Grammar rules: unitarity, depth, width

Every closed-system gate in the diagram must satisfy $U^{†}U=I$. A drawn box whose matrix fails that test is not a valid isolated quantum gate, whatever the documentation says. Measurement plays by different rules: it emits a classical outcome and changes the state description, so it is not a unitary box and cannot be undone by drawing another box.

Two numbers belong to every circuit reading. Width is the number of wires the program needs. Depth is the number of sequential gate layers once dependencies are respected. A clean diagram may have modest abstract depth while compilation raises the physical depth sharply — a device with a different native gate set or sparse connectivity forces decompositions and swaps. Depth and width are part of what the diagram says, not merely part of the performance postmortem.

Worked example: tracing a Bell circuit

Take the two-qubit program from the figure:

q0: |0> -- H -- ctrl -- M -> c0
q1: |0> ------- X ----- M -> c1

Expanded into instructions:

1. Start in $|00⟩$.
2. Apply H to q0: the state becomes $\frac{|00⟩+|10⟩}{\sqrt{2}}$.
3. Apply CNOT with q0 as control and q1 as target: the target flips only on the branch where the control is 1, giving $\frac{|00⟩+|11⟩}{\sqrt{2}}$.
4. Measure both wires in the computational basis: 00 or 11, each with probability $\frac{1}{2}$.

This is exactly the reasoning pattern a statevector simulator automates: map initialization, gate application, controlled operations, and sampling back to linear algebra. If you can do step three by hand, you understand entanglement operationally, not just rhetorically.

Where the intuition fails

The first trap is reading each wire as a log line holding a definite bit. A wire is a component of a joint state. A gate on one wire rewrites amplitudes across the whole statevector, and a controlled gate can entangle wires that previously factored — after the CNOT above, asking "what is q0's value?" no longer has an answer.

The second trap is treating SDK output as final truth. A simulator trace shows ideal circuit semantics. Compiled hardware execution adds basis changes, swaps, calibration choices, and noise. The diagram is the starting specification, not the whole engineering story.

The engineering view

The closest classical analog is a typed intermediate representation with unusual semantics. Registers have width. Instructions have arity. Some instructions commute; others must stay ordered. Measurement writes classical bits, and later operations may be classically controlled on those bits.

When a circuit gives the wrong answer, debug by layer:

• Diagram syntax — did you draw what you meant?
• Gate sequence — does the expansion match the drawing, with control and target in the right places?
• Ideal statevector trace — does the math produce the intended state?
• Compiled circuit — did transpilation blow up the depth or reorder what must stay ordered?
• Hardware result — do the counts match the compiled circuit within sampling noise?

A syntax mistake is a different failure from a swapped control-target convention; a correct ideal trace can still fail after transpilation if depth grows too large; a correct compiled circuit can still produce poor counts on noisy hardware. Naming the layer is half the fix.

What this buys you in diligence

When you review a tool, a vendor demo, or an internal prototype, ask for the circuit at three levels: abstract circuit, transpiled circuit, and measurement interpretation. A serious claim can state width, depth, gate set, control conventions, and how the raw counts are decoded into answers. If the team cannot trace a small circuit by hand on a whiteboard, the larger benchmark is not ready for your trust.

Exercise

Trace before you run. Work the Bell circuit from the figure without touching a keyboard first.

• Trace: write the state after initialization, after H, after CNOT, and the measurement probabilities at the end.
• Submit: a short annotated trace mapping each circuit symbol to an instruction and each instruction to a state update.
• Check: run the same circuit in any simulator and confirm the sampled counts match your trace within sampling noise.
• Repair: if you lost the basis order, swapped control and target, or treated measurement as another unitary, redo Chapter 13 (Tensor Products and State-Space Growth) before moving on.

Check your understanding

Answer without notes: translate a small circuit diagram into a gate sequence and predict the final state before running any code.

A passing answer keeps the basis ordering explicit, applies controlled gates to the joint state rather than to individual wires, and reserves classical bits for after the measurement symbols.

Oral defense: explain why measurement cannot be drawn as just another unitary box — what would go wrong in the trace if it were?

If you get stuck

If your traces drop basis ordering, amplitude updates, or the distinction between correlation and control, work back through Chapter 13 (Tensor Products and State-Space Growth). Circuit notation is a user interface over that mathematics.