Circuit Cost: Depth, Width, Gate Set, Connectivity

Five numbers that define a circuit's cost

An abstract circuit states the intended computation. A runnable circuit has to fit a device or a simulator, and the distance between those two objects is where most overclaims live. Five quantities measure the distance:

• Width. How many qubits the circuit occupies.
• Depth. How many layers of gates must run sequentially.
• Gate set. Whether the operations are native to the hardware or must be decomposed.
• Connectivity. Whether qubits that need to interact are physically or logically adjacent.
• Measurement structure. When quantum state becomes classical evidence, and how often that readout is wrong.

Judging a circuit means pricing all five. Optimizing one in isolation usually just moves the cost to another.

Routing and error: the two multipliers

First, routing. When a circuit demands an interaction between qubits that are not adjacent, the compiler inserts swap chains or reroutes the logic, and the depth you drew is not the depth you get:

Second, errors accumulate per gate. A rough teaching model:

This is deliberately crude — real noise models are richer — but it makes the operative point: two circuits computing the same function can carry wildly different risk. Two-qubit gates, readout error, idle time, and crosstalk usually dominate the budget, so the cheaper circuit is the one with fewer expensive operations, not fewer boxes on the page.

Worked example: the shallower circuit loses

Two implementations of the same small task:

• Circuit A: width 5, abstract depth 20, twelve two-qubit gates, needs several nonlocal interactions.
• Circuit B: width 6, abstract depth 28, eight two-qubit gates, laid out to match the device connectivity.

On paper, A wins. Now compile both for the actual device. A's nonlocal interactions cost eighteen extra swap-related layers; B routes for free:

B also exposes fewer two-qubit gates to the error budget. Deeper on paper, cheaper in reality — and the deciding evidence was the device's connectivity map, not the circuit's elegance. The right choice depends on the execution target, which is why the circuit as drawn is never the whole story.

Where the accounting fails

The classic failure is algorithm-name-as-evidence. "We ran Grover" or "the demo uses QFT" says nothing about qubits, depth, native gates, connectivity, shots, noise, or the classical baseline. The name is the one part of the claim that carries no cost information.

The subtler failure is treating transpilation as formatting — a reprint of the same circuit in a new notation. Transpilation changes depth, gate counts, scheduling, and measurement layout. It preserves meaning, but it can flip the practical verdict on a specific device, which is why resource claims should always quote the compiled circuit, not the source.

Compiler thinking for circuit review

This is systems work. A high-level description lowers through an intermediate representation to target-specific instructions; each target produces a different compiled form; each optimization trades one cost against another. Anyone who has read a compiler's output assembly will find the situation familiar.

The deliverable that turns a drawing into an engineering artifact is a cost table:

• abstract qubits, and physical or logical qubits after mapping;
• abstract depth and transpiled depth;
• one-qubit and two-qubit gate counts;
• measurement count;
• connectivity assumption;
• error or fidelity assumption;
• classical baseline.

If a claim cannot fill in most of those rows, it is not yet a circuit claim — it is a schedule of intentions.

Asking for the cost table

When a startup, research group, or internal team claims a circuit-level advantage, request the table before engaging with the narrative. Then stress it: does the advantage survive routing? Finite precision? The error budget? The classical baseline?

If the advantage evaporates under any of those, the honest recommendation is monitor or wait, whatever the demo looked like. If the table is transparent and survives sensitivity checks, the claim has earned deeper review — and the team has demonstrated they know what they are selling.

Exercise

A transpilation depth memo. Take one small abstract circuit and document how its width, depth, gate set, and connectivity assumptions change when mapped to a specific target layout. End with a one-line recommendation — build, monitor, wait, or avoid — under your stated assumptions.

• Submit: a memo with the table — abstract depth, routing depth, effective depth, two-qubit gate count — and the dominant failure mode you identified.
• Check: apply the routing formula and the simple error-budget model to both versions, and state which you would actually run.
• Repair: if the memo treats transpilation as cosmetic or never counts two-qubit gates, rebuild your circuit-tracing discipline with Chapter 19 (Multi-Qubit Circuits) before doing resource estimates.

Check your understanding

Given two equivalent circuits, compare them on depth, two-qubit gate count, and connectivity fit for a stated device, and defend the safer choice in three sentences.

Oral defense: a colleague shows a clean, shallow circuit diagram as evidence a workload is hardware-ready. What do you ask for, and why is the diagram insufficient?

If you get stuck

If your cost memos do not connect circuit structure to gate scope, routing, and measurement evidence, return to Chapter 19 (Multi-Qubit Circuits) and Chapter 16 (Circuit Notation as a Programming Language). Cost analysis is circuit tracing with stakes; the tracing has to be automatic first.