The Full Quantum Computer Stack

The job contract: estimate one phase#

Fix a small phase-estimation input, output precision, success probability, and classical verification condition.

A quantum computer is a layered system that converts a classical problem into a fragile physical process and back into trustworthy classical information. The path:

A quantum computer comprises integrated algorithm, compilation, control, device, measurement, and classical-processing layers. [full-stack-review] [silicon-digital-qpu]

Trace one phase-estimation result without skipping a representation#

Start with a contract the machine can fail: estimate an eigenphase to $m$ binary digits with an accepted-result probability of at least $1-\varepsilon$, given a state-preparation procedure and a classically checkable relation. The algorithm record names the unitary $U$, its controlled powers, approximation tolerance, and shot or repetition policy. If $U$ is itself a compiled simulation, that implementation and its approximation error are upstream inputs; the stack cannot treat the controlled operation as a free box.

The circuit representation expands those requirements into registers, controlled operations, inverse Fourier operations, measurements, and classical conditions. Record logical qubit count, operations by type, dependency depth, and the point at which a measurement result is consumed. Preserve the phase convention and bit ordering. A compiler can produce a circuit that is unitary-equivalent under one ordering while post-processing interprets the bits in another, yielding a precise but wrong phase.

End-to-end acceptance: Run the same declared input often enough to estimate both result quality and operational variance. Partition failures by boundary: invalid problem instance, compiler rejection, scheduling conflict, control abort, missing measurement, classifier rejection, decode failure, and final validation failure. Report successful answers per submitted job and per wall-clock hour in addition to conditional accuracy. The distinction catches systems that look excellent only after excluding infrastructure failures. Repeat with a second, intentionally simple instance whose answer is independently computable; this control separates a pipeline regression from difficulty inherent in the target instance. Finally, rebuild the trace from stored artifacts on a clean environment. Every derived field should be reproducible without access to undocumented provider state, or it must be labeled as an external observation with timestamp and request identifier.

Compiler outputs a timed target program#

Carry logical qubits/gates through native decomposition, layout, routing, scheduling, and calibration identifiers.

Every arrow hides an assumption, and any assumption can be the one that fails. The stack is the machine; the chip is one component of it.

Physical implementation requires initialization, coherent control, measurement, and scalable interconnection under explicit criteria. [divincenzo-criteria]

Compilation adds target assumptions and costs#

The target description specifies native operations, coupling graph, durations, error metadata, measurement groups, and control constraints. Decomposition replaces ideal controlled powers with native sequences. Placement maps logical to physical qubits; routing inserts motion or swaps; scheduling resolves resource conflicts. Save the before/after operation counts, critical-path duration, mapping, target version, random seed, and compiler version. “Transpiled successfully” is not a resource account.

Equivalence checks should occur before noisy execution. For a small fixture, compare unitaries up to global phase or compare action on a complete basis. For larger controlled evolutions, use structural invariants, reference simulation on reduced instances, and property tests. Scheduling then needs a separate check: equivalent gates can still overlap resources illegally or use calibrations outside their validity window.

Controls realize an analog trajectory#

Map scheduled instructions to pulses/lasers/fields with durations, bandwidth, crosstalk, and drift assumptions.

Their product is the trap: a circuit that looks shallow in a textbook can grow too deep after routing, too slow after control timing, or too noisy after measurement and reset. Depth, time, and topology are not three concerns; they are one budget wearing three hats.

Fault-tolerant execution adds repeated syndrome extraction, decoding, and logical-operation resources to the stack. [google-surface-code-below-threshold] [google-surface-code-below-threshold]

Instructions become analog trajectories#

A scheduled operation selects calibrated pulses, laser patterns, flux trajectories, or measurement windows. Each has amplitude, phase, frequency, envelope, duration, and hardware channel assignments. The controller must bind the instruction to the calibration identified by the compiler or explicitly revalidate it. A symbolic two-qubit gate therefore crosses an interface where digital semantics meet an analog Hamiltonian and where crosstalk, leakage, distortion, and drift enter.

Timing must include reset, synchronization, conditional branches, and guard intervals. The shortest pulse is not necessarily the shortest reliable schedule: a faster envelope may leak outside the computational subspace, while simultaneous operations may interfere. Store both requested and realized timing. The integrated nature of compilation, control, device, measurement, and classical processing is why full-stack analyses cannot be replaced by a chip specification [full-stack-review].

The device returns voltages, photons, or counts#

Trace physical measurement through analog electronics and classifiers rather than jumping directly to bits.

Take a small phase-estimation routine built from repeated controlled operations, and walk it down the stack. The algorithm requires controlled evolution that preserves phase information long enough to matter. The circuit layer turns that into controlled gates plus an inverse Fourier transform. The compiler asks whether the target device offers the needed two-qubit interactions directly or must insert routing — on a sparsely connected chip, the routing layers arrive before control limits are even considered. The control layer asks whether the pulses fit calibration windows and coherence time. Readout asks whether the outcomes are trustworthy enough to reconstruct a phase. Post-processing asks whether the final distribution supports the original claim.

Benchmark conclusions require the task, execution layer, uncertainty, and classical comparison to remain visible end to end. [benchmarking-2025]

The device does not return bits#

Physical readout produces a voltage trace, photon arrival record, charge signal, or another analog observation. A chain of amplification, filtering, digitization, integration, and classification turns that record into a bit and perhaps a confidence value. Record classifier version, assignment-error calibration, integration window, rejected records, and correlations across simultaneously measured qubits. If mitigation or readout correction is applied, retain the raw counts as well as the transformed estimate.

In a fault-tolerant execution, many measurements are syndromes rather than algorithm outputs. They feed a decoder that updates a frame or requests an action; only after that process does the system have a logical measurement. Current experiments showing below-threshold surface-code correction are primary evidence that this loop can exhibit improved logical behavior under declared conditions, not evidence that arbitrary workloads inherit the same rate [google-surface-code-below-threshold].

Decoding and post-processing restore the contract#

Show where syndrome decoding, result aggregation, uncertainty, and classical phase inference enter.

A useful trace names at least one failure mode per layer, and it ends with a gate: the next measurable result that would raise confidence in the weakest layer — say, reliable execution of the deepest controlled-operation block on the real topology, with settings published so others can reproduce it.

Current stack parameters and integration claims require dated review rather than transfer from a generic architecture diagram. [full-stack-review] [google-surface-code-below-threshold]

Classical inference closes the original contract#

Phase-estimation post-processing maps measured bit strings to phase candidates, handles endianness, aggregates repetitions, and applies the acceptance test. It should report uncertainty or empirical coverage, not just the most frequent string. If the eigenstate preparation is imperfect, multiple phases may be present; the conclusion must distinguish algorithmic sampling from readout error. The final result links back to the original $m$-bit and success-probability requirement.

Classical validation can recompute a small instance, verify an algebraic consequence, or compare independent estimates. Benchmarking discipline requires the task, baseline, uncertainty, and complete execution boundary to remain visible [benchmarking-2025]. A hybrid verifier that silently performs most of the useful computation changes the claim; report its cost and information access.

An end-to-end ledger exposes interface losses#

Publish one row per boundary with input/output type, owner, latency, error, evidence, and version/date.

Cloud access is not evidence of stack maturity. Renting time on a machine is excellent for learning and benchmarking. It proves nothing about whether the system can carry a useful workload or a fault-tolerant roadmap.

A quantum computer comprises integrated algorithm, compilation, control, device, measurement, and classical-processing layers. [full-stack-review] [silicon-digital-qpu]

A boundary ledger makes losses inspectable#

Use one row per transition: problem to algorithm, algorithm to circuit, circuit to target program, program to controls, controls to device trajectory, trajectory to analog record, record to classified data, data to decoded logical result, and result to decision. Each row names input type, output type, owner, version, latency, error contribution, evidence, and a reject condition. An absent unit or version makes the row incomplete.

For the synthetic trace, compilation takes 0.040 seconds, queueing 0.200, control 0.006, readout 0.003, and decoding 0.004. The total is 0.253 seconds and queueing dominates this record. That arithmetic does not make queueing a universal bottleneck; it proves that the ledger preserves terms which a kernel-only timing would omit. Replace one value at a time with sourced observations and rerun the sensitivity analysis.

Use failure injection to verify boundary ownership#

A clean end-to-end run proves only one path. Replay the trace after changing one contract at a time: reverse the measurement-bit map, expire the calibration, delay the decoder result beyond its consumer, drop a readout record, and change the target graph after compilation. The responsible boundary should reject the artifact and name the mismatched version or invariant. If the final answer merely becomes worse, the system lacks a detectable contract.

Archive the original problem record, circuit, compiled mapping, timed schedule, control identifier, raw observations, classifier output, decoder events, post-processing configuration, and acceptance result under one trace ID. Hash large artifacts and preserve software and schema versions. A reader should be able to recompute the 0.253-second synthetic total and replace any hypothetical row with an observation without editing unrelated layers.

The proof gate is a repeated run across a meaningful calibration interval. Report variation in compilation output, queueing, realized control timing, readout classification, and final success. A stack is not integrated merely because its components connected once; it is integrated when interface changes are detected, failures are attributable, and the result contract remains testable over operation.

Close the trace with an error-and-time reconciliation#

The phase-estimation trace needs two ledgers that meet at the acceptance test. The timing ledger begins with controlled-evolution blocks and includes routing, pulse schedules, measurement integration, reset, decoding, queueing, and classical phase reconstruction. Parallel operations contribute to the critical path rather than being summed as if sequential; serialized shared resources appear explicitly. The failure ledger allocates the accepted-result budget among imperfect eigenstate preparation, synthesis, physical operations, readout, decoding, and finite-sampling uncertainty. A union bound can be a planning approximation, but correlated calibration or coherent errors need their own model.

Reconciliation means regenerating the final result from boundary records, not trusting a total copied into a summary. The classified bit string must preserve the compiler’s bit significance through inverse-QFT output and classical reconstruction. The declared controlled power must match the scheduled operation, and any approximation tolerance used in synthesis must be included in the algorithmic error allowance. Injecting a reversed register or stale calibration should cause a typed failure, not merely move the reported phase.

The last row states what has actually been demonstrated. A synthetic trace proves schema compatibility and arithmetic. A simulator run adds evidence about the modeled noise and schedule. Hardware samples add evidence only for the named backend, calibration interval, inclusion policy, and shots. Keeping these evidence classes attached to the same trace prevents an architectural diagram from being mistaken for an implemented end-to-end machine.