Silicon Spin Qubits
Silicon spin qubits rest on the most seductive sentence in quantum hardware: the industry that prints billions of transistors could print qubits. This chapter shows where that analogy holds, where it breaks, and what evidence separates a single good device from a manufacturable processor.
Semiconductor manufacturing is a genuine advantage for spin qubits, but it is an advantage in search of uniformity: the fabrication that makes transistors interchangeable must make qubits behave identically, and that is a much higher bar.
By the end of this chapter you will be able to write a spin-qubit modality note that traces an abstract gate down to a spin in a quantum dot, names the variability and readout problems honestly, and states proof gates that would convince a skeptic.
Core concepts: quantum dots, exchange control, device variability, cryogenic wiring, modality proof gates.
A transistor's quantum cousin
A silicon spin qubit stores quantum information in the spin of a single electron — or sometimes a nucleus — trapped in a tiny puddle of charge called a quantum dot, formed by metal gates on a silicon device. Spins are small, potentially dense, and can have long coherence times because spin couples weakly to the electrical noise that plagues charge-based qubits. And they are made, roughly speaking, with the tools of the semiconductor industry.
That last fact drives the entire investment thesis. Silicon fabrication is the most refined manufacturing capability humanity operates: atomic-layer control, enormous volumes, decades of yield learning. If qubits can ride even part of that infrastructure, the scaling curve that classical chips enjoyed might partially transfer to quantum processors.
The caution is equally structural. Compatibility with semiconductor manufacturing is not the same thing as a demonstrated quantum computer. Spin control, device variability, readout, charge noise, yield, cryogenic operation, wiring, calibration, and error-correction support each get a vote. The modality thesis pairs a real manufacturing upside with a demanding control and quality problem.
The physics under the gate
Every spin-qubit gate is a piece of controlled Hamiltonian dynamics: . Depending on the implementation, is shaped by local magnetic field gradients, microwave pulses, or the exchange interaction that couples neighboring electrons when their wavefunctions overlap. The abstract gate in a circuit diagram is only the target; the delivered gate is whatever this analog physics actually does, with its own speed, error, and drift.
The timing budget is the same one every modality faces: . Spin coherence can be long, but the useful question is never a single number. It is whether initialization, high-quality operations, measurement, reset, and recalibration fit inside the coherent window — across every dot in a large array, not just the best device in the paper.
That qualifier matters because of variability. Two transistors that differ slightly still switch. Two quantum dots that differ slightly have different resonance frequencies, different coupling strengths, and different control calibrations. Manufacturing spread that a classical chip absorbs becomes, in a quantum chip, a per-qubit control problem that someone or something has to solve and keep solved.
Worked example: tracing a scaling roadmap
Suppose a roadmap claims a straight path from semiconductor fabrication to dense quantum processors. A stack trace starts at the desired logical operation and walks down: How is a spin initialized? How is it controlled, and at what fidelity? How do two neighboring spins couple, and what about non-neighboring ones? How is the spin read out — charge sensors are the usual answer — and how fast? How is the device reset and recalibrated? Does the fabrication process deliver uniform dots or a distribution of devices, and who tunes the ones at the tail of the distribution?
The evidence list for a serious modality note includes coherence times, gate and readout fidelities, yield, measured variability across dies, calibration load per qubit, wiring density into the cryostat, and integration with the control electronics. A strong proof gate is not a bigger array photograph. It is sustained operation quality and readout across a growing manufactured array, with variability and yield reported explicitly rather than averaged away.
Where the analogy breaks
The classic trap is the syllogism: silicon scaled classical computing, these qubits are silicon, therefore these qubits will scale. The manufacturing base is relevant — it buys density, process control, and ecosystem knowledge — but quantum control imposes tolerances that classical design rules never had to meet, and the proof requirements are different in kind.
The second trap is laundering a beautiful device-level result into a processor-level claim. A two-qubit demonstration in one carefully selected device is physics. A processor is device physics plus reproducible fabrication plus control electronics plus compiler mapping plus error correction. A memo that does not say which layer has been proven has not yet said anything falsifiable.
The software view: a leaky abstraction
For a computer scientist, spin qubits are a case study in abstraction leakage. A logical-qubit interface wants to hide spin resonance frequencies, charge sensors, exchange pulses, and calibration schedules. But if every dot on the chip needs different control parameters, and those parameters drift, then compilation and calibration are part of the programming model whether the API admits it or not.
This is like writing code for heterogeneous hardware, one level down. The same instruction label can carry different cost, noise, and scheduling constraints at different sites on the same chip, and those constraints change over time. The expert skill is reading the calibration and architecture assumptions underneath a circuit-level result before trusting it.
What this buys you in diligence
A strong memo names the upside without blushing: density, manufacturing learning curves, integration with classical control electronics, and an ecosystem that knows how to yield-improve a hard process. Then it names the kill criteria with equal clarity: poor dot-to-dot uniformity, readout that does not scale, wiring that cannot reach a large array, calibration burden that grows faster than the qubit count, or operation quality that collapses outside hero devices.
The decision — build, partner, invest, monitor — should hang on proof gates tied to those criteria, not on the manufacturing analogy alone. The analogy tells you where the tailwind is; it cannot tell you whether the boat floats.
Exercise
Write a spin-qubit modality note. Take a real spin-qubit result or roadmap and work it through the stack.
- Trace: from one abstract two-qubit gate down to spin control, coupling, readout, fabrication, and back up to the scaling claim.
- Evidence: list coherence, gate fidelity, readout fidelity, yield, variability, wiring, and calibration evidence — and mark what is missing.
- Gates: define three proof gates and two kill criteria for the claimed scaling path.
- Decide: choose build, partner, invest, monitor, wait, or avoid, and state what evidence would flip your label.
Check your understanding
Answer without notes: why does transistor-level manufacturing success not automatically transfer to spin qubits?
A passing answer explains that transistors tolerate variation that qubits cannot, names variability and readout as first-order problems, and distinguishes a device result from a processor result. Oral defense: pitch spin qubits to a skeptic in two minutes, then give the skeptic's rebuttal in one.
If you get stuck
If your note treats manufacturing promise, or a single elegant device, as proof of scalable logical computation, revisit Chapter 55, Superconducting Qubits. That chapter establishes the modality-note discipline — control, readout, scaling path, kill criteria — that this chapter applies to silicon, and rebuilding the note from that template usually exposes the missing layer.