Orientation guide
Hardware Architecture and the Full Stack
A quantum computer is six systems stacked on top of each other, and the qubits are only one of them. This guide walks the stack from application down to device and back up through measurement and decoding, then tours the major hardware modalities with their real strengths and bottlenecks.
In this chapter 13 sections
Reader question. Which layers must cooperate for an abstract quantum circuit to become a reliable measured result?
The circuit must pass through algorithm, compilation, logical control, physical instruction, analog control, device, readout, decoding, and classical post-processing layers; the slowest or least reliable translation can dominate regardless of raw qubit count.
- This guide does not crown a hardware modality or publish a current vendor leaderboard.
- It does not imply that metrics measured under different protocols are directly comparable.
A round trip, not a chip
Trace intent down to pulses and records back to an answer.
A quantum computer is the whole path from problem statement to classical answer; application, algorithm, circuit, compiler, control system, physical qubits, measurement, decoder, and classical post-processing. Every layer transforms the one above it, and every layer can independently kill the workload.
| Layer | The question it answers |
|---|---|
| Application | What useful problem is being solved? |
| Algorithm | What quantum structure gives an advantage? |
| Circuit | How many qubits, gates, depth, and measurements? |
| Compiler | How does the circuit map to native gates and connectivity? |
| Runtime | How are jobs scheduled, batched, and measured? |
| Control | Which pulses, lasers, voltages, or optical operations implement the gates? |
| QPU | What physical system stores the quantum information? |
| Measurement | How is quantum information converted to classical bits? |
| Decoder | How are errors inferred and corrected? |
| Classical HPC and AI | What classical compute supports simulation, optimization, decoding, and workflow integration? |
Evidence boundary. A useful quantum computer is a full system whose layers include control, compilation, error correction, and classical processing. [Full-stack architecture review] [National Academies systems assessment]
The contracts between adjacent layers
Name what each layer consumes, emits, and can invalidate.
Raw qubit count is one metric among many, and rarely the binding one. The numbers that actually predict whether a workload runs:
- one-qubit and two-qubit gate fidelity
- measurement fidelity
- reset fidelity and speed
- coherence times
- gate times
- connectivity
- crosstalk
- leakage
- calibration stability
- uptime and queue time
- compiled circuit depth
- logical error rate
- reliable logical operations
- cost per useful result
Notice the ordering of this list as you read vendor materials: the metrics near the top are measured per device; the ones near the bottom are measured per system. Serious roadmaps migrate downward over time.
Superconducting qubits
Strengths: fast gates, a mature fabrication and control ecosystem borrowed from semiconductor engineering, and broad cloud availability.
Bottlenecks: coherence, crosstalk, wiring and cryogenics, fabrication yield, and scaling the qubit count while preserving fidelity.
Trapped ions
Strengths: high gate fidelities, long coherence, and flexible connectivity within a trap.
Bottlenecks: gate speed, scaling across modules, photonic interconnects between traps, and system cost per unit of throughput.
Neutral atoms
Strengths: large arrays, reconfigurable geometry, natural analog simulation, and promising parallelism for error-correction cycles.
Bottlenecks: high-fidelity digital gates, atom loss and movement errors, continuous operation, and the depth of error-correction cycles.
Photonics
Strengths: networking comes naturally, some components run at room temperature, and there is a credible semiconductor-style manufacturing path with a long-term fault-tolerance vision.
Bottlenecks: photon loss, source and detector performance, switching, resource overhead, and integrating enormous component counts.
Silicon spin qubits
Strengths: compatibility with semiconductor manufacturing, a tiny physical footprint, and the prospect of genuine density.
Bottlenecks: control complexity, device variability, coupling and readout, and scaling with high yield.
Cat, bosonic, and topological routes
Strengths: the promise of cutting error-correction overhead by building protection or error bias into the hardware itself.
Bottlenecks: complete logical gate sets, high-quality two-qubit operations, independent validation of the underlying claims, and system integration.
Evidence boundary. Physical implementation criteria include controllable qubits, gates, measurement, and scalable interconnection. [David P. DiVincenzo] [T. D. Ladd et al.]
Depth becomes time on a topology
Compile one small circuit against limited connectivity.
Compilation maps an ideal circuit onto real hardware, and in doing so it can change gate count, depth, error exposure, measurement placement, routing, native gate usage, and schedule length. A circuit that looks short in a textbook can become unrunnable after compilation to a sparse topology. This is why Part V treats the transpiler as part of the algorithm, not as plumbing beneath it.
The control layer is where symbolic gates become physical actions: microwave pulses for superconducting qubits, laser pulses for ions and atoms, optical components for photonics, magnetic and electric fields for spins. It has to manage timing, amplitude, phase, calibration, feedback, synchronization, and low-latency correction; continuously, and at scale.
Once error correction enters the picture, the control stack and decoder stop being accessories and become part of the computer. Their throughput and latency bound how fast correction cycles can run, which bounds everything else.
Evidence boundary. Connectivity and native operations can increase compiled circuit depth relative to the abstract circuit. [openqasm3] [Lieven M. K. Vandersypen et al.]
Notation contract: Logical qubits q_i are distinct from physical device elements; use D_abstract and D_mapped; state native gate set and topology.
Control and readout share the reliability budget
Expose calibration, reset, measurement, and decoder dependencies.
Quantum output is classical data, so readout quality caps everything the machine can report. The questions: How accurate is readout? How fast? Is mid-circuit measurement supported? Can qubits be reset quickly for reuse? Does measuring one qubit disturb its neighbors? Can the data feed real-time control?
Mid-circuit measurement and fast reset deserve special attention: without them, the correction cycles from the previous guide cannot run at all.
Quantum hardware reaches users through public cloud platforms, private deployments, on-premise systems, national lab and HPC centers, and hybrid data centers. The access model is not a commercial footnote; it changes the engineering:
- Cloud favors access, ecosystem, and queue-based throughput.
- On-prem favors sovereignty and deep integration with a customer's own systems.
- HPC integration favors scientific workflows with classical pre- and post-processing.
- Data-center integration favors enterprise operations and scheduling discipline.
A modality map organized by bottleneck
Route readers to detailed hardware dossiers without ranking slogans.
- Pick one modality and write its top three strengths and top three bottlenecks from memory.
- Explain why two-qubit gate fidelity matters more than one-qubit fidelity for most circuits.
- Take a CNOT-heavy circuit and show how limited connectivity inflates its depth.
- Explain why mid-circuit measurement matters for error correction.
- Compare cloud access and on-premise deployment from a customer-adoption perspective.
- Write a one-page hardware diligence memo for one company, using the checklist above.
Full-stack trace dossier
| Field | Reader-visible record |
|---|---|
| Format | Layered machine-readable trace plus topology-aware compiled circuit |
| Verification | Validator accounts for every operation before and after routing, maps each stage to an owner, and reconciles final counts with the declared circuit. |
| Availability | Source-embedded acceptance record; no separate download is claimed |
{
"artifact": "Full-stack trace dossier",
"format": "Layered machine-readable trace plus topology-aware compiled circuit",
"acceptance_test": "Validator accounts for every operation before and after routing, maps each stage to an owner, and reconciles final counts with the declared circuit.",
"publication_state": "source-embedded contract and worked fixture"
}Scope boundary
- This guide does not crown a hardware modality or publish a current vendor leaderboard.
- It does not imply that metrics measured under different protocols are directly comparable.
Depth commitment. Nine layer contracts, one topology mapping, and a bottleneck-oriented modality map.
Practice problem
Map a four-qubit circuit onto a line topology, inserting necessary swaps and assigning every compiled operation to a stack layer.
Logical circuit: H q0; CNOT q0,q3; CNOT q3,q2; measure q0,q2.
Hardware graph: q0--q1--q2--q3.
Count every SWAP as three native CNOTs; restore the initial logical layout before measurement.- Deliverable
- An abstract circuit, mapped circuit, depth comparison, and layer ownership table.
- Pass condition
- A reference mapper verifies connectivity legality and recomputes both operation count and depth.
Verification record
Expected solution form. Annotated mapped circuit plus a machine-generated resource diff.
Model answer. One valid restored-layout trace moves logical q0 along the line with SWAP(0,1), SWAP(1,2), applies CX(2,3), and reverses the two SWAPs before the requested measurements. Every compiled two-qubit edge is adjacent; four SWAPs contribute twelve native CNOTs in addition to the logical entanglers.
Model result and check. The validation script rejects nonadjacent two-qubit gates and matches the submitted depth.
Acceptance test. A reference mapper verifies connectivity legality and recomputes both operation count and depth.
Provenance
Sources and review
- Lieven M. K. Vandersypen et al.. A look at the full stack. Nature Reviews Physics. 2021peer-reviewed perspective
- National Academies of Sciences, Engineering, and Medicine. Quantum Computing: Progress and Prospects. National Academies Press. 2019consensus study report
- David P. DiVincenzo. The physical implementation of quantum computation. Fortschritte der Physik. 2000primary peer-reviewed perspective
- T. D. Ladd et al.. Quantum computers. Nature. 2010peer-reviewed review
- OpenQASM Technical Steering Committee. OpenQASM 3 specification. Linux Foundation Joint Development Foundation. 2026official technical specification
The load-bearing claims in the chapter are mapped inline to this registered source set. A citation supports only the bounded claim beside it.